Wafer level semiconductor package and manufacturing methods thereof

ABSTRACT

A semiconductor package includes at least one semiconductor die having an active surface, an interposer element having an upper surface and a lower surface, a package body, and a lower redistribution layer. The interposer element has at least one conductive via extending between the upper surface and the lower surface. The package body encapsulates portions of the semiconductor die and portions of the interposer element. The lower redistribution layer electrically connects the interposer element to the active surface of the semiconductor die.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to semiconductor packages andmanufacturing methods thereof. More particularly, the invention relatesto a wafer level semiconductor package and manufacturing methodsthereof.

2. Description of Related Art

Semiconductor devices have become progressively more complex, driven atleast in part by the demand for smaller sizes and enhanced processingspeeds. To support increased functionality, semiconductor packagesincluding these devices often have an large number of contact pads forexternal electrical connection, such as for inputs and outputs. Thesecontact pads can occupy a significant amount of the surface area of asemiconductor package.

In the past, wafer level packaging could be restricted to a fan-inconfiguration in which electrical contacts and other components of aresulting semiconductor device package can be restricted to an areadefined by a periphery of a semiconductor device. To address theincreasing number of contact pads, wafer level packaging is no longerlimited to the fan-in configuration, but can also support a fan-outconfiguration. For example, in a fan-out configuration, contact pads canbe located at least partially outside an area defined by a periphery ofa semiconductor device. The contact pads may also be located on multiplesides of a semiconductor package, such as on both a top surface and abottom surface of the semiconductor package.

However, forming and routing the electrically connections from asemiconductor device to this increasing number of contact pads canresult in greater process complexity and cost. It is against thisbackground that a need arose to develop the wafer level semiconductorpackage and related methods described herein.

SUMMARY OF THE INVENTION

One aspect of the invention relates to a semiconductor package. In oneembodiment, the semiconductor package includes at least onesemiconductor die having an active surface, an interposer element havingan upper surface and a lower surface, a package body, and a lowerredistribution layer. The interposer element has at least one conductivevia extending between the upper surface and the lower surface. Thepackage body encapsulates portions of the semiconductor die and portionsof the interposer element. The lower redistribution layer electricallyconnects the interposer element to the active surface of thesemiconductor die.

In another embodiment, the semiconductor package includes at least onesemiconductor die having an active surface, an interposer element havingan upper surface and a lower surface, a package body, a lowerredistribution layer, and an electrical contact exposed from a lowerperiphery of the semiconductor package. The interposer element has atleast one conductive via extending between the upper surface and thelower surface. The package body encapsulates portions of thesemiconductor die and portions of the interposer element. The lowerredistribution layer electrically connects the interposer element to theactive surface of the semiconductor die, and electrically connects theelectrical contact to the active surface of the semiconductor die andthe interposer element. The lower redistribution layer is disposedadjacent to the active surface of the semiconductor die.

Another aspect of the invention relates to a method of forming asemiconductor package. In one embodiment, the method includes providinga semiconductor die having an active surface, and placing an interposerelement adjacent to the die. The interposer element has an upper surfaceand a lower surface, and has at least one first conductive via extendingto the lower surface. The method further includes encapsulating portionsof the semiconductor die and portions of the interposer element with anencapsulant such that the active surface of the semiconductor die, thelower surface of the interposer element, and portions of the encapsulantform a substantially coplanar surface. The method further includesforming a lower redistribution layer on the substantially coplanarsurface, the lower redistribution layer electrically connecting theinterposer element to the active surface of the semiconductor die.

Other aspects and embodiments of the invention are also contemplated.The foregoing summary and the following detailed description are notmeant to restrict the invention to any particular embodiment but aremerely meant to describe some embodiments of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross section view of a stacked package assembly, accordingto an embodiment of the invention;

FIG. 2 is a top cross section view of a semiconductor package in a planeA-A shown in FIG. 1, according to an embodiment of the invention;

FIG. 3 is a cross section view of various conductive via embodimentswithin an interposer;

FIGS. 4A through 4B are cross section views of a portion of asemiconductor package including an interposer, according to anembodiment of the invention;

FIG. 5 is a bottom view of an interposer, according to an embodiment ofthe invention;

FIG. 6 is a cross section view of a semiconductor device including viasexposed adjacent to a back surface of the semiconductor device,according to an embodiment of the invention;

FIG. 7 is a top cross section view of a semiconductor package, accordingto an embodiment of the invention; and

FIG. 8A through FIG. 8G are views showing a method of forming asemiconductor package, according to an embodiment of the invention.

The drawings illustrate embodiments of the invention and, together withthe description, serve to explain the principles of some embodiments ofthe invention. Reference will now be made in detail to some embodimentsof the invention, examples of which are illustrated in the accompanyingdrawings. Wherever possible, the same reference numbers are used in thedrawings and the descriptions to refer to the same or like features.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1, a cross section view is shown of a stacked packageassembly 100 according to an embodiment of the invention. The stackedpackage assembly 100 includes a semiconductor package 192 and asemiconductor package 194 positioned above the semiconductor package192. The semiconductor package 194 is electrically connected to thesemiconductor package 192 through conductive bumps 193. It iscontemplated that the semiconductor package 194 may be any form ofsemiconductor package, such as a wafer-level package, a BGA package, anda substrate-level package. The semiconductor package 194 may alsoinclude a combination of one or more semiconductor packages and/or oneor more passive electrical components. The semiconductor package 192includes a semiconductor device 102, which includes a lower surface 104which in the illustrated embodiment is an active surface, i.e. theactive surface having die bond pads 111, an upper surface 106, andlateral surfaces 108 disposed adjacent to a periphery of thesemiconductor device 102 and extending between the lower surface 104 andthe upper surface 106. In the illustrated embodiment, each of thesurfaces 104, 106, and 108 is substantially planar, with the lateralsurfaces 108 having a substantially orthogonal orientation with respectto the lower surface 104 or the upper surface 106, although it iscontemplated that the shapes and orientations of the surfaces 104, 106,and 108 can vary for other implementations. In one embodiment, the uppersurface 106 is a back surface of the semiconductor device 102, while thelower surface 104 is an active surface of the semiconductor device 102.The lower surface 104 may include the die bond pads 111 that provideinput and output electrical connections for the semiconductor device 102to conductive structures included in the package 192, such as apatterned conductive layer 150 (described below). In the illustratedembodiment, the semiconductor device 102 is an integrated circuit,although it is contemplated that the semiconductor device 102, ingeneral, can be any active device including for example an optical orother type of sensor, a micro electro-mechanical system (MEMS), anypassive device, or a combination thereof. The semiconductor device 102may be an active die. While one semiconductor device is shown in thesemiconductor package 192, it is contemplated that more than onesemiconductor device can be included in the semiconductor package 192for other implementations.

As shown in FIG. 1, the package 192 also includes a package body 114that is disposed adjacent to the semiconductor device 102. In theillustrated embodiment, the package body 114 covers or encapsulatesportions of the semiconductor device 102 and portions of one or moreinterposers 170, such as interposer elements 170 (described below). Thepackage body 114 can provide mechanical stability as well as protectionagainst oxidation, humidity, and other environmental conditions. In thisembodiment, the package body 114 substantially covers the upper surface106 and the lateral surfaces 108 of the semiconductor device 102, withthe lower surface 104 of the semiconductor device 102 beingsubstantially exposed or uncovered by the package body 114. The packagebody 114 includes a lower surface 116 and an upper surface 118. In theillustrated embodiment, each of the surfaces 116 and 118 issubstantially planar, although it is contemplated that the shapes andorientations of the surfaces 116 and 118 can vary for otherimplementations.

In one embodiment, the package body 114 can be formed from a moldingmaterial. The molding material can include, for example, a Novolac-basedresin, an epoxy-based resin, a silicone-based resin, or another suitableencapsulant. Suitable fillers can also be included, such as powderedSiO₂. The molding material may be a pre-impregnated (prepreg) material,such as a pre-impregnated dielectric material.

The package 192 further includes the one or more interposers 170. Theinterposer(s) 170 may be positioned adjacent to a perimeter 177 (i.e., alateral periphery, see FIG. 2) of the semiconductor device 102. Theinterposer 170 may be a contiguous interposer that extends around theperimeter 177 of the semiconductor die (see FIG. 7) or may beuncontiguous, discrete interposer elements as shown in FIG. 2. Eachinterposer 170 is comprised of a substrate material that can be glass,silicon, a metal, a metal alloy, a polymer, or another suitablestructural material. The interposers 170 in the package 192 can beformed from the same material, or from different materials. In oneembodiment, each interposer 170 may define one or more openings 171extending from a lower surface 172 of the interposer 170 to an uppersurface 173 of the interposer 170. A conductive via 174 is formed ineach of the openings 171.

Referring to FIGS. 1 and 2, the interposer 170 may include a pluralityof conductive vias 174. In one embodiment, a conductive via 174A isformed in each opening 171, and may be exposed at the lower surface 172and the upper surface 173. In another embodiment, a conductive via 174Bmay protrude beyond the lower surface 172 and the upper surface 173.Further embodiments of the conductive vias are illustrated in FIG. 3.The conductive via 174 may be directly connected to the patternedconductive layer 150. The conductive via 174 may include an innerconductive interconnect 275. The inner conductive interconnect 275 is aconductive element that may be formed from a metallic material,typically by plating, conductive paste, or other methods known to thoseof ordinary skill in the art. Depending upon the substrate material of asubstrate portion 271 of the interposer 170, the conductive via 174 mayinclude an outer dielectric layer 282 of dielectric material formedbetween the inner conductive interconnect 275 and the substrate 271 (seeFIGS. 2 and 3). The outer dielectric layer 282 may be in the form of anannular insulator.

In one embodiment, the diameter of the conductive via 174 may be in therange from about 10 μm to about 50 μm, such as from about 10 μm to about20 μm, and from about 20 μm to about 50 μm. For diameters of theconductive via 174 in the range from about 10 μm to about 20 μm, thestructure of conductive vias 174B can be used. For diameters of theconductive via 174 in the range from about 20 μm to about 50 μm, thestructure of conductive vias 174A can be used.

The package 192 may include one or more redistribution layers (RDL) 151,where each RDL includes the patterned conductive layer 150 and adielectric (or passivation) layer 130. The patterned conductive layercan be formed from copper, a copper alloy, or other metals. Theredistribution layer 151 may be disposed adjacent (e.g., on, near, oradjoining) to the active surface 104 of the semiconductor device 102,and to the lower surface 116 of the package body 114. The redistributionlayer 151 may include only the patterned conductive layer 150, or may bemulti-layered. For example, in addition to the dielectric layer 130 andthe patterned conductive layer 150, the redistribution layer 151 mayinclude a dielectric layer 131 such that the patterned conductive layer150 is disposed between the dielectric layers 130 and 131. It iscontemplated that more or less dielectric layers may be used in otherimplementations. Each of the dielectric layers 130 and 131 can be formedfrom a dielectric material that is polymeric or non-polymeric. Forexample, at least one of the dielectric layers 130 and 131 can be formedfrom polyimide, polybenzoxazole, benzocyclobutene, or a combinationthereof. The dielectric layers 130 and 131 can be formed from the samedielectric material or different dielectric materials. For certainimplementations, at least one of the dielectric layers 130 and 131 canbe formed from a dielectric material that is photoimageable orphotoactive.

The patterned conductive layer 150 may extend through openings 136 inthe dielectric layer 130 to electrically connect to the conductive vias174, and through openings 146 in the dielectric layer 130 toelectrically connect to the die bond pads 111. Package contact pads 175for electrical connection outside of the stacked package assembly 100may be formed from portions of the patterned conductive layer 150exposed by openings 137 in the dielectric layer 131.

In one embodiment, the package 192 may provide a two-dimensional fan-outconfiguration in which the patterned conductive layer 150 extendssubstantially laterally outside of the periphery 177 (see FIG. 2) of thesemiconductor device 102. For example, FIG. 1 shows electrical contacts,including conductive bumps 190, at least partially outside the lateralperiphery 177 (see FIG. 2) of the semiconductor device 102. Theconductive bumps 190 may be exposed from a lower periphery 195 of thepackage 192. This allows the semiconductor package 192 to beelectrically connected to devices external to the semiconductor package192 via the redistribution layer 151 and the conductive bumps 190. Theconductive bumps 190 may be electrically connected to the semiconductordevice 102 via the patterned conductive layer 150, and may be disposedadjacent to the package contact pads 175. The conductive bumps 190 maybe electrically connected to the interposers 170 via the patternedconductive layer 150.

The conductive vias 174 included in the interposer 170 can facilitateextending a two-dimensional fan-out to a three-dimensional fan-outand/or fan-in by providing electrical pathways from the semiconductordevice 102 to electrical contacts, including the conductive bumps 193.The conductive bumps 193 may be exposed from an upper periphery 196 ofthe package 192. This allows the semiconductor package 192 to beelectrically connected to devices external to the semiconductor package192 via the redistribution layer 153 and the conductive bumps 193. Theconductive bumps 193 may be electrically connected to upper contact pads176. The upper contact pads 176 may be formed from portions of apatterned conductive layer 152 included in a redistribution layer 153that is disposed adjacent to the upper surface 118 of the package body114. The patterned conductive layer 152 may be disposed between adielectric (or passivation) layer 132 and a dielectric layer 133. Thepatterned conductive layer 152 may extend through openings 139 in thedielectric layer 132 to electrically connect to the conductive vias 174.The upper contact pads 176 may be formed from portions of the patternedconductive layer 152 exposed by openings 138 in the dielectric layer133. The redistribution layer 153 may have similar structuralcharacteristics to those previously described for the redistributionlayer 152.

In one embodiment, the redistribution layer 153 may not include thedielectric layer 132, so that the patterned conductive layer 152 and thedielectric layer 133 may be adjacent to the upper surface 118 of thepackage body 114. In this embodiment, the patterned conductive layer 152is also adjacent to the interposer 170, so in this embodiment theinterposer 170 should be made of a non-conductive material such asglass. Alternatively, the interposer 170 can include a first portionformed of a material such as silicon and a second portion formed of anon-conductive material such as glass or some other dielectric material,on long as the patterned conductive layer 152 is adjacent to thenon-conductive portion of the interposer 170.

In one embodiment, a three-dimensional fan-out configuration can becreated by electrically connecting conductive bump 193A to thesemiconductor device 102 through the patterned conductive layer 152, theconductive vias 174, and the patterned conductive layer 150.Alternatively or in addition, a three-dimensional fan-in configurationcan be created by electrically connecting conductive bump 193B to thesemiconductor device 102 through the patterned conductive layer 152, theconductive vias 174, and the patterned conductive layer 150. Thesethree-dimensional fan-out and/or fan-in configurations canadvantageously increase flexibility beyond that provided bytwo-dimensional fan-out in terms of the arrangement and spacing ofelectrical contacts both above the upper surface 118 of the package body114, and below the lower surface 116 of the package body 114. This canreduce dependence upon the arrangement and spacing of the contact padsof the semiconductor device 102. In accordance with a fan-outconfiguration, the conductive bump 193A is laterally disposed at leastpartially outside of the periphery of the semiconductor device 102. Inaccordance with a fan-in configuration, the conductive bump 193B islaterally disposed within the periphery of the semiconductor device 102.It is contemplated that the conductive bumps 190 and 193, in general,can be laterally disposed within that periphery, outside of thatperiphery, or both, so that the package 100 may have a fan-outconfiguration, a fan-in configuration, or a combination of a fan-out anda fan-in configuration. In the illustrated embodiment, the conductivebumps 190 and 193 may be solder bumps, such as reflowed solder balls.

The patterned conductive layer 150, the conductive vias 174, and thepatterned conductive layer 152 can be formed from a metal, a metalalloy, a matrix with a metal or a metal alloy dispersed therein, oranother suitable electrically conductive material. For example, at leastone of the patterned conductive layer 150, the conductive vias 174, andthe patterned conductive layer 152 can be formed from aluminum, copper,titanium, or a combination thereof. The patterned conductive layer 150,the conductive vias 174, and the patterned conductive layer 152 can beformed from the same electrically conductive material or differentelectrically conductive materials.

FIG. 2 is a top cross section view of the semiconductor package 192 in aplane A-A shown in FIG. 1, according to an embodiment of the invention.The cross section view shows discrete interposer elements 170 disposedon each of the four sides of the semiconductor die 102 and encapsulatedin the package body 114. The discrete interposer elements 170 may bedisposed inwardly from a lateral periphery 115 of the package body 114.The package body 114 may extend around a lateral periphery 178 of eachof the interposer elements 170, such that the lateral periphery 178 ofeach of the interposer elements 170 is embedded in the package body 114.Also illustrated are portions of the conductive vias 174 associated withthe interposers 170, such as the inner conductive interconnects 275 andthe outer dielectric layers 282 disposed adjacent to the innerconductive interconnects 275 in some embodiments. The outer dielectriclayer 282 may in the form of an annular insulator. The inner conductiveinterconnects 275 can be made of conductive materials similar to thoseused to form portions of the conductive via 174 described with referenceto FIG. 1. The outer dielectric layer 282 can be made of materialssimilar to those used to form the dielectric layers 130 and 131described with reference to FIG. 1. The cross section view also showsthe upper surface 106 of the die 102. In this embodiment, unusedconductive vias 174 may be left electrically unconnected.

The discrete interposer elements 170 can be singulated from aninterposer wafer such that the interposer elements 170 have varyingsizes and shapes based on the number and positions of through viaconnections required for any given semiconductor package (see FIG. 8B).This approach provides the flexibility to enable manufacturing ofmultiple package types with different numbers and positions of throughvia connections from the same interposer wafer. In addition, theinterposer elements 170 can be sized to correspond to each package typeso that unused through via connections are reduced or eliminated. Sincethere is no need, for example, to form a custom substrate for eachpackage type to reduce the amount of unused substrate area, thisapproach can reduce manufacturing cost and complexity.

In addition, since the discrete interposer elements 170 may be smallrelative to the package body 114, the discrete interposer elements 170may have little or no effect on the coefficient of thermal expansion(CTE) of the package 192. Instead, the CTE of the package body 114 canbe adjusted to better match the CTE of the semiconductor device 102, andtherefore to increase reliability. For example, filler content of themold compound used to form the package body 114 can be adjusted so thatthe CTE of the package body 114 more closely matches the CTE of thesemiconductor device 102.

FIG. 3 is a cross section view of various conductive via embodimentswithin the interposer 170. In one embodiment, the interposer 170 definesthe opening 171, and includes the conductive via 174A at least partiallydisposed in the opening 171, where the conductive via 174A includes theinner conductive interconnect 275A. The conductive via 174A may be athrough silicon via (TSV). The conductive via 174A includes innerconductive interconnect 275A exposed at the upper surface 173 and thelower surface 172 of the interposer 170, and the outer dielectric layer282 surrounding the inner conductive interconnect 275A. The outerdielectric layer 282 may be disposed adjacent to a lateral surface 381of the opening 171. In this embodiment, the outer dielectric layer 282and the inner conductive interconnect 275A may substantially fill theopening 171.

In another embodiment, the conductive via 174B includes an innerconductive interconnect 275B that protrudes beyond the upper surface 173and the lower surface 172 of the interposer 170. In this embodiment, theouter dielectric layer 282 may also protrude beyond the upper surface173 and the lower surface 172. A conductive layer 383 may be disposedadjacent to protruding portions of the inner conductive interconnect275B and the outer dielectric layer 282.

In a further embodiment, a conductive via 174C includes an innerconductive interconnect 275C that is an annular plating layer, and theouter dielectric layer 282. The inner conductive interconnect 275C maydefine an opening 384. Alternatively, the inner conductive interconnect275C may be filled by an inner dielectric layer (not shown).

In a further embodiment, a conductive via 174D includes an innerconductive interconnect 275D that is disposed directly adjacent to thesubstrate 271 of the interposer 170. In this embodiment, the interposer170 is made of a non-conductive material such as glass. The innerconductive interconnect 275D may define an opening (not shown) similarto the opening 384.

In other respects, the conductive vias 174A, 174B, 174C, and 174D aresimilar to the conductive via 174 and perform a similar function ofrouting I/O from the top package 194 to the bottom package 192 and tothe conductive bumps 190 to distribute I/O outside the package 100 toother devices (see FIG. 1).

Employment of interposers 170 to provide electrical connectivity betweena redistribution layer adjacent to an upper surface of a semiconductorpackage (such as the redistribution layer 153 of FIG. 1) and aredistribution layer adjacent to a lower surface of a semiconductorpackage (such as the redistribution layer 151 of FIG. 1) may result inreduced via diameter compared to other approaches. For example, theconductive vias 174 may have a diameter in the range from about 10 μm toabout 50 μm, such as in the range from about 10 μm to about 20 μm, about20 μm to about 30 μm, or in the range from about 30 μm to about 50 μm.These diameters are smaller than a typical diameter (greater than 75 μm)of through package vias, which may be formed by laser drilling through amold compound. Because of the reduced diameter of the conductive vias174, corresponding capture pads for the conductive vias 174, such asportions of the patterned conductive layers 150 and 152 of FIG. 1, canbe of reduced size and pitch. This results in higher densityredistribution routing traces, such as between the die 102 and theinterposers 170, and may enable routing to be performed without addingadditional redistribution layers. The reduced diameter of eachconductive via 174 can also can allow for higher connectivity densitythan would be possible with the larger laser-drilled vias through themold compound. In addition, because of their smaller diameter, theconductive vias 174 can be easier to fill with conductive and/ornon-conductive material while avoiding undesirable effects such asprocessor solution and polymer leakage and entrapment.

FIGS. 4A through 4B are cross section views of a portion of asemiconductor package 400 including an interposer 470, according to anembodiment of the invention. The semiconductor package 400 and theinterposer 470 are generally similar to the semiconductor package 192and the interposer 170 of FIG. 1, except that the interposer 470includes a conductive interconnect 440. Referring to FIG. 4A, in oneembodiment of a semiconductor package 400A, the conductive interconnect440 may be disposed on and extend substantially laterally along a lowersurface 472A of an interposer 470A. In this embodiment, a dielectriclayer 441 is disposed between the conductive interconnect 440 and thesubstrate 271 of the interposer 470A. Referring to FIG. 4B, in oneembodiment of a semiconductor package 400B, the conductive interconnect440 may be disposed on and extend substantially laterally along a lowersurface 472B of an interposer 470B. In this embodiment, the conductiveinterconnect 440 is adjacent to the substrate 271 of the interposer4708, so in this embodiment the interposer 470B should be made of anon-conductive material such as glass. Alternatively, the interposer470B can include a first portion formed of a material such as siliconand a second portion formed of a non-conductive material such as glassor another dielectric material, so long as the conductive interconnect440 is adjacent to the non-conductive portion of the interposer 470B.

One advantage of the conductive interconnect 440 is that the conductiveinterconnect 440 can serve as an additional trace layer forredistribution trace routing, which can reduce the number ofredistribution layers in the semiconductor package 400 needed for thispurpose. A reduction in the number of redistribution layers in thesemiconductor package 400 can result in reduced manufacturing processcomplexity and cost. In addition, the conductive interconnect 440 can beburied under a redistribution layer, and therefore does not take upspace on an external surface of the semiconductor package 402.

In the embodiments of FIGS. 4A and 4B, a semiconductor device (such asthe semiconductor device 102 of FIG. 1) is electrically connected to theupper redistribution layer 153 through the patterned conductive layer150 included in a lower redistribution layer 151, the conductiveinterconnect 440, and the conductive via 174 included in the interposer470. The lower redistribution layer 151 may cover the conductiveinterconnect 440. Alternatively, a protective layer (not shown) may bedisposed between the conductive interconnect 440 and the lowerredistribution layer 151. In one embodiment, the conductive interconnect440 may electrically connect the semiconductor device 102 to a passiveelectrical component (see FIG. 5).

Referring to FIG. 4B, in one embodiment, the dielectric layer 132 (seeFIG. 1) may be omitted from the upper redistribution layer 153, so thatthe patterned conductive layer 152 is disposed adjacent to the substrate271 of the interposer 470B. In this embodiment, the interposer 470B ismade of a non-conductive material such as glass.

FIG. 5 is a bottom view of the interposer 470, according to anembodiment of the invention. The interposer 470 includes multipleconductive vias 174 (such as conductive vias 174D and 174E) and multipleconductive interconnects 440. The conductive interconnects 440 may forma routing layer. In one embodiment, the routing layer is on the lowersurface of the interposer 470. The conductive interconnects 440 mayconnect the conductive via 174D to the conductive via 174E. In oneembodiment, the conductive via 174D may provide electrical connectivitythrough a semiconductor package such as the semiconductor package 400 ofFIGS. 4A and 4B, while the conductive via 174E may provide electricalconnectivity to a patterned conductive layer such as the patternedconductive layer 150. The conductive interconnects 440 may allow forcrossing over of conductors during redistribution layer routing byrouting across the interposer 470 on a surface of the interposer 470.

In one embodiment, the conductive interconnects 440 may electricallyconnect the conductive vias 174 to one or more passive electricalcomponents known to one of ordinary skill in the art, such as a resistor500, an inductor 502, and a capacitor 504. These passive electricalcomponents, like the conductive interconnects 440, are disposed on thelower surface 472 of the interposer 470.

FIG. 6 is a cross section view of a semiconductor device 602 includingconductive vias 608 exposed adjacent to a back surface 606 of thesemiconductor device 602, according to an embodiment of the invention.The semiconductor device 602 is in most respects similar to thesemiconductor device 102 of FIG. 1, except for the conductive vias 608.The conductive vias 608 are similar to the conductive vias 174. Oneadvantage of the conductive vias 608 is that the conductive vias 608 areformed in the semiconductor device 602. This can reduce or eliminate theneed for separate interposers, which can save space in a semiconductorpackage such as the semiconductor package 192 of FIG. 1. In oneembodiment, the conductive via 608 can electrically connect thesemiconductor device 602 to a redistribution layer such as theredistribution layer 153 of FIG. 1. The conductive via 608 mayelectrically connect a die bonding pad 611 to circuitry external to thesemiconductor device 602, such as the conductive layer 152 (see FIG. 1)included in the redistribution layer 153. Alternatively or in addition,the conductive via 608 may electrically connect circuitry 610 internalto the semiconductor device 602 to circuitry external to thesemiconductor device 602, such as the conductive layer 152 included inthe redistribution layer 153.

FIG. 7 is a top cross section view of a semiconductor package 700,according to an embodiment of the invention. The cross section viewshows an interposer 770 surrounding a package body 714 encapsulating thesemiconductor device 102. The cross section view shows conductive vias774 associated with the interposer 770. The semiconductor package 700 isin most respects similar to the semiconductor package 192 described withreference to FIG. 1 except for the shape of the interposer 770. In thisembodiment, the interposer 770 is a contiguous interposer extendingaround the lateral periphery 177 of the semiconductor die 102. Inparticular, the conductive vias 774 and the package body 714 are similarto the conductive vias 174 and the package body 114 described withreference to FIG. 1.

The interposer 770 defines an opening 772 substantially tilled with thepackage body 714. The package body 714 can decouple the semiconductorpackage 700 from any stresses imposed by the interposer 770. In thisembodiment, unused conductive vias 774 may be left electricallyunconnected.

FIG. 8A through FIG. 8G are views showing a method of forming asemiconductor package, according to an embodiment of the invention. Forease of presentation, the following manufacturing operations aredescribed with reference to the package 192 of FIG. 1. However, it iscontemplated that the manufacturing operations can be similarly carriedout to form other semiconductor packages that may have differentinternal structure from the package 192. In addition, it is contemplatedthat these manufacturing operations can form an array of connectedsemiconductor packages that can be separated, such as throughsingulation, to form multiple individual semiconductor packages.

FIG. 8A shows an interposer wafer (or interposer panel) 800. Theinterposer wafer 800 can be formed from glass, silicon, a metal, a metalalloy, a polymer, or another suitable structural material. Theinterposer wafer 800 includes conductive vias 804 that are similar tothe conductive vias 174 of FIGS. 1 through 3. In one embodiment, theconductive vias 804 may extend entirely through the interposer wafer800, and may protrude beyond an interposer 870. The interposer 870 maybe a discrete, uncontiguous interposer element. Alternatively, theconductive vias 804 may be exposed at a lower surface 806 of theinterposer wafer 800, but may extend only partially through theinterposer wafer 800. The shape of the interposer wafer 800 may becircular, rectangular, square, or any other shape determined to befeasible for manufacturing operations by one of ordinary skill in theart.

Next, FIG. 8B shows the interposer 870. The interposer 870 may beseparated from the interposer wafer 800, such as by singulationincluding singulation methods known to those of ordinary skill in theart such as saw singulation. One advantage of separating the interposer870 from the interposer wafer 800 is that a standard size interposerwafer or panel 800 is can be used. The interposer wafer 800 can besingulated into interposers of varying sizes and shapes based on thenumber and positions of through via connections required for any givensemiconductor package. The conductive vias 804 may extend entirelythrough the interposer 870, and may protrude beyond the interposer 870.Alternatively, as described for the interposer wafer 800 of FIG. 8A, theconductive vias 804 may extend only partially through the interposer870.

Next, FIG. 8C shows a molded structure 810. In one embodiment, the die102 and one or more of the interposers 870 are disposed adjacent to acarrier 812. Advantageously, the die 102 and the interposers 870 areplaced or located on the carrier using commercially available pick andplace and/or die attach equipment. The die 102 and the interposers 870may be attached to the carrier 812 by an adhesive layer 814. In oneembodiment, the interposer 870 includes a conductive via 874A that isexposed at a lower surface 872 of the interposer 870. In anotherembodiment, the interposer 870 includes a conductive via 874B thatprotrudes beyond the lower surface 872 into the adhesive layer 814.Then, the die 102 and the interposers 870 are encapsulated by moldingmaterial to form the molded structure 810. The molding material maysurround a lateral periphery 878 of the interposer 870. The moldedstructure 810 is made of materials similar to those forming the packagebody 114 of FIG. 1. The molded structure 810 can be formed using any ofa number of molding techniques, such as transfer molding, injectionmolding, or compression molding. To facilitate proper positioning of themolded structure 810 during subsequent singulation operations, fiducialmarks can be formed in the molded structure 810 by various methods, suchas laser marking.

Next, FIG. 8D shows a molded structure 820. The molded structure 820 isformed by first removing the molded structure 810 from the carrier 812in FIG. 8C. Then, a redistribution layer including the redistributionlayer 151 (see FIG. 1) is formed adjacent to the active surface 104 ofthe die 102, the lower surface 816 of the package body 817, and thelower surface 872 of each of the interposers 870. A dielectric materialis applied using any of a number of techniques, such as printing,spinning, or spraying, and is then patterned to form a dielectric layerincluding the dielectric layer 130 (see FIG. 1). As a result ofpatterning, the dielectric layer 130 is formed with openings, includingopenings that are aligned with the active surface 104 and sized so as toat least partially expose the die bond pads 111 of the semiconductordevice 102. In one embodiment, the dielectric layer further includesopenings that are aligned and sized so as to at least partially exposethe conductive vias 874A. In another embodiment, the dielectric layerincludes openings through which the conductive vias 874B extend.Patterning of the dielectric material to form the dielectric layer 130can be carried out in any of a number of ways, such as photolithography,chemical etching, laser drilling, or mechanical drilling, and theresulting openings can have any of a number of shapes, such as acylindrical shape, such as a circular cylindrical shape, an ellipticcylindrical shape, a square cylindrical shape, or a rectangularcylindrical shape, or a non-cylindrical shape, such as a cone, a funnel,or another tapered shape. It is also contemplated that lateralboundaries of the resulting openings can be curved or roughly textured.

An electrically conductive material is then applied to the dielectriclayer 130 and drawn into the openings defined by the dielectric layer130 using any of a number of techniques, such as chemical vapordeposition, electroless plating, electrolytic plating, printing,spinning, spraying, sputtering, or vacuum deposition, and is thenpatterned to form an electrically conductive layer including thepatterned conductive layer 150 (see FIG. 1). As a result of patterning,the patterned conductive layer 150 is formed with electricalinterconnects that extend laterally along certain portions of thedielectric layer 130 and with gaps between the electrical interconnectsthat expose other portions of the dielectric layer 130. The patternedconductive layer 150 included in the redistribution layer 151 may beelectrically connected to the die bond pads 111 and the conductive vias874. Patterning of the electrically conductive layer 150 can be carriedout in any of a number of ways, such as photolithography, chemicaletching, laser drilling, or mechanical drilling.

A dielectric material is then applied to the patterned conductive layer150 and the exposed portions of the dielectric layer 130 using any of anumber of techniques, such as printing, spinning, or spraying, and isthen patterned to form a dielectric layer including the dielectric layer131 (see FIG. 1). As a result of patterning, the dielectric layer 131 isformed with openings that are aligned with the electrically conductivelayer 150, including openings that are aligned so as to at leastpartially expose the electrically conductive layer 150 and are sized soas to accommodate solder bumps. Patterning of the dielectric material131 can be carried out in any of a number of ways, such asphotolithography, chemical etching, laser drilling, or mechanicaldrilling, and the resulting openings can have any of a number of shapes,including a cylindrical shape, such as a circular cylindrical shape, anelliptic cylindrical shape, a square cylindrical shape, or a rectangularcylindrical shape, or a non-cylindrical shape, such as a cone, a funnel,or another tapered shape. It is also contemplated that lateralboundaries of the resulting openings can be curved or roughly textured.

Next, FIG. 8E shows a molded structure 830. In one embodiment, a portionof each interposer 870 is removed to form the interposers 170, alongwith a portion of the molding material. This is typically done bybackgrinding, CMP, or other techniques resulting in a substantiallycoplanar surface 832.

In an alternative embodiment to FIG. 8E, FIG. 8F shows a moldedstructure 840. The molded structure 840 is similar to the moldedstructure 830 of FIG. 8E, except that additional backgrinding or otherremoval techniques are performed to expose the back surface 606 of thesemiconductor die 602, resulting in a substantially coplanar surface 836between the die 602, the package body 114, and the interposer 170. Inone embodiment, if the die corresponds to the die 602 of FIG. 6, enoughmolding material is removed to expose the back surface 606 of the die602 and the conductive interconnects 610 (see FIG. 6).

Next, FIG. 8G shows the semiconductor package 192 of FIG. 1. To form thesemiconductor package 192, a redistribution layer 153 is formed adjacentto an upper surface 832 of the molded structure 830 (see FIG. 8E). Theredistribution layer 153 is formed similarly to the redistribution layer151, and is electrically connected to the conductive vias 174. In oneembodiment, singulation is next carried out along the dashed lines 890to separate the semiconductor packages 192.

While the invention has been described and illustrated with reference tospecific embodiments thereof, these descriptions and illustrations donot limit the invention. It should be understood by those skilled in theart that various changes may be made and equivalents may be substitutedwithout departing from the true spirit and scope of the invention asdefined by the appended claims. The illustrations may not be necessarilybe drawn to scale, and that there may be other embodiments of thepresent invention which are not specifically illustrated. Thus, thespecification and the drawings are to be regarded as illustrative ratherthan restrictive. Additionally, the drawings illustrating theembodiments of the present invention may focus on certain majorcharacteristic features for clarity. Furthermore, modifications may bemade to adapt a particular situation, material, composition of matter,method, or process to the objective, spirit and scope of the invention.All such modifications are intended to be within the scope of the claimsappended hereto. In particular, while the methods disclosed herein havebeen described with reference to particular operations performed in aparticular order, it will be understood that these operations may becombined, sub-divided, or re-ordered to form an equivalent methodwithout departing from the teachings of the invention. Accordingly,unless specifically indicated herein, the order and grouping of theoperations are not limitations of the invention.

1. A semiconductor package, comprising: at least one semiconductor diehaving an active surface; an interposer element having an upper surfaceand a lower surface, the interposer element having at least oneconductive via extending between the upper surface and the lowersurface; a package body encapsulating portions of the semiconductor dieand portions of the interposer element; and a lower redistribution layerthat electrically connects the interposer element to the active surfaceof the semiconductor die.
 2. The semiconductor package of claim 1,further comprising an upper redistribution layer adjacent to the uppersurface of the interposer element.
 3. The semiconductor package of claim2, further comprising an electrical contact exposed from an upperperiphery of the semiconductor package, wherein the electrical contactelectrically connects another semiconductor package to the upperredistribution layer.
 4. The semiconductor package of claim 1, wherein:the conductive via includes an inner conductive interconnect and anouter dielectric layer surrounding the inner conductive interconnect;and the inner conductive interconnect is exposed at the lower surface ofthe interposer element to electrically connect with the lowerredistribution layer.
 5. The semiconductor package of claim 1, wherein:the conductive via includes an inner conductive interconnect and anouter dielectric layer surrounding the inner conductive interconnect;and the inner conductive interconnect protrudes beyond the lower surfaceof the interposer element to electrically connect with the lowerredistribution layer.
 6. The semiconductor package of claim 2, wherein:the conductive via includes an inner conductive interconnect and anouter dielectric layer surrounding the inner conductive interconnect;and the inner conductive interconnect is coplanar with the upper surfaceof the interposer element to electrically connect with the upperredistribution layer.
 7. The semiconductor package of claim 1, whereinthe interposer element is one of a plurality of discrete interposerelements positioned around a lateral periphery of the semiconductor die.8. The semiconductor package of claim 7, wherein each of the pluralityof discrete interposer elements is disposed inwardly from a lateralperiphery of the package body.
 9. The semiconductor package of claim 1,wherein the interposer element includes a routing layer extendinglaterally along a lower surface of the interposer element.
 10. Thesemiconductor package of claim 9, wherein the routing layer includes apassive electrical component adjacent to the lower surface of theinterposer element, wherein the routing layer electrically connects thepassive electrical component to the at least one conductive via.
 11. Asemiconductor package, comprising: at least one semiconductor die havingan active surface; an interposer element having an upper surface and alower surface, the interposer element having at least one conductive viaextending between the upper surface and the lower surface; a packagebody encapsulating portions of the semiconductor die and portions of theinterposer element; a lower redistribution layer that electricallyconnects the interposer element to the active surface of thesemiconductor die; and an electrical contact exposed from a lowerperiphery of the semiconductor package, wherein: the lowerredistribution layer electrically connects the electrical contact to theactive surface of the semiconductor die and the interposer element; andthe lower redistribution layer is disposed adjacent to the activesurface of the semiconductor die.
 12. The semiconductor package of claim11, further comprising an upper redistribution layer adjacent to theupper surface of the interposer element.
 13. The semiconductor packageof claim 12, further comprising another semiconductor packageelectrically connected to the upper redistribution layer.
 14. Thesemiconductor package of claim 11, wherein the interposer element is oneof a plurality of discrete interposer elements positioned around alateral periphery of the semiconductor die.
 15. The semiconductorpackage of claim 14, wherein the package body extends around a lateralperiphery of each of the plurality of discrete interposer elements. 16.A method of forming a semiconductor package, comprising: providing asemiconductor die having an active surface; placing an interposerelement adjacent to the die, the interposer element having an uppersurface and a lower surface, the interposer element having at least onefirst conductive via extending to the lower surface; encapsulatingportions of the semiconductor die and portions of the interposer elementwith an encapsulant such that the active surface of the semiconductordie, the lower surface of the interposer element, and portions of theencapsulant form a substantially coplanar surface; and forming a lowerredistribution layer on the substantially coplanar surface, the lowerredistribution layer electrically connecting the interposer element tothe active surface of the semiconductor die.
 17. The method of claim 16,further comprising removing a portion of the interposer element toexpose the first conductive via at the upper surface of the interposerelement.
 18. The method of claim 16, wherein encapsulating portions ofthe semiconductor die and portions of the interposer element includessurrounding a lateral periphery of the interposer element with theencapsulant.
 19. The method of claim 18, wherein: the semiconductor diedefines a second conductive via extending from the active surface to aback surface of the semiconductor die; and the second conductive via iselectrically connected to the semiconductor die and the upperredistribution layer.
 20. The method of claim 18, wherein the firstconductive via includes an inner conductive interconnect and an outerdielectric layer surrounding the inner conductive interconnect, theinner conductive interconnect being coplanar with the upper surface ofthe interposer element, and further comprising electrically connectingthe inner conductive interconnect with the upper redistribution layer.